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On this page

  • TL;DR: claimed vs verified
  • What is CoWoS and why does it set the price of AI chips?
  • What can we actually verify?
  • The capacity and lead-time numbers
  • A short history of CoWoS price talk
  • Why this matters even if the exact number is wrong
  • What this means for what you build or pay
  • How to check this story yourself
  • Bottom line
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TSMC CoWoS 20% Price Hike Report: What Is Claimed and What Is Verified

TSMC, AI Chips, AI Infrastructure, Semiconductors, Supply Chain

Part of AI Chips and Infrastructure

A report says TSMC will raise CoWoS packaging prices up to 20%. TSMC has not confirmed it. What we can verify, what we cannot, and what it means for AI chip costs.

Oct 27, 2026·8 min read·Yash Thakker
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TSMC CoWoS 20% Price Hike Report: What Is Claimed and What Is Verified

A report that TSMC will raise prices for its CoWoS advanced packaging by up to 20% spread on X on October 26, 2026, tied to longer equipment lead times and AI demand. As of writing, TSMC has not confirmed any figure, and the one price report we can trace to a named outlet is smaller and about something else. This post lays out the claim, the evidence, and why packaging prices matter to anyone who pays for AI compute.

If you want the wider picture first, our roundup of AI chip supply chain news from TSMC, Samsung and GlobalFoundries covers how packaging has become the choke point.

TL;DR: claimed vs verified

table · 3 cols
ClaimWhere it comes fromStatus
TSMC plans up to a 20% CoWoS price increaseSupply-chain sources, repeated by accounts on X on Oct 26Not confirmed by TSMC; no named outlet we could open
TSMC will raise chipmaking prices up to 10% from 2027Nikkei Asia, relayed by Reuters on July 21, 2026Reported; TSMC declined to confirm or deny
Packaging equipment lead times stretched to 6 to 8 monthsA post on X citing a reportUnverified; a July rumor gave 7 to 9 months
Monthly CoWoS capacity above 130,000 wafers in 2026 and 200,000 in 2027Investment-banker estimates cited on XEstimates, not TSMC guidance
CoWoS expanding beyond GPUs to server CPUs and custom ASICsIndustry commentaryPlausible and consistent with earlier coverage

What is CoWoS and why does it set the price of AI chips?

CoWoS is the packaging step that joins a processor die to stacks of high-bandwidth memory (HBM) on a silicon interposer. Most data-center AI accelerators go through it. Even when wafers are available, a chip cannot ship without packaging, so capacity here has repeatedly limited how many accelerators reach customers.

Three trays carrying a chip along a short track, illustrating the TSMC CoWoS packaging supply chainThree trays carrying a chip along a short track, illustrating the TSMC CoWoS packaging supply chain

We looked at that bottleneck earlier in our post on Nvidia's first US-made GB300 chips, Arizona and Amkor packaging, which showed that even US-fabbed wafers still needed packaging steps elsewhere. The demand side keeps widening: the report we are examining says CoWoS is now used beyond GPUs, for server CPUs and custom ASICs, which means more customers competing for the same lines.

What can we actually verify?

The Nikkei report is the anchor. Reuters relayed Nikkei Asia's July 21, 2026 story: TSMC plans to raise chipmaking prices by up to 10% from 2027, with base increases of 5% to 10% depending on customer and product, and up to 10% on mature nodes such as 12nm, 16nm and 28nm. Negotiations reportedly ran from June to July. A TSMC spokesperson said, "Our pricing strategy is strategic, not opportunistic."

TaiwanPlus reported on July 22 that TSMC declined to confirm or deny the report and said it does not comment on pricing. It also noted that AMD and Intel have already raised prices this year. In June, according to the Reuters-relayed report, CEO C.C. Wei said he would like to raise prices but would avoid the abrupt hikes some memory makers imposed.

The 20% CoWoS number is a different claim. We found no October 2026 article from a named outlet that ties a 20% figure to TSMC's CoWoS pricing. What we found instead:

  • A November 2024 TrendForce item, headlined CoWoS prices may rise 20%, cited a Morgan Stanley report of a 10% to 20% range as ASE and Amkor competed for outsourced orders, an earlier cycle with the same headline number.
  • A July 2026 industry note said ASE, the largest outsourced packaging provider, had reportedly raised advanced packaging quotes by more than 20%. That is ASE, not TSMC.
  • A September 2026 supply-chain report put TSMC's 2027 increase at about 3% to 6%, with more for advanced processes.

So a 20% figure is circulating and has precedent, but the current version rests on unnamed supply-chain sources and social posts. It could be a real new plan, a rerun of the 2024 story, or a mix of the ASE number with TSMC's wafer pricing. We cannot tell which, and we are not going to pick one.

The capacity and lead-time numbers

The same posts cite monthly CoWoS capacity above 130,000 wafers in 2026 and 200,000 by 2027, attributed to investment bankers, and say TSMC Chairman C.C. Wei stated that packages five times the size of the largest printable chip are already in mass production. Treat these separately:

  • The capacity figures match earlier estimates. A June TrendForce report had TSMC's own 2026 capacity at 120,000 to 140,000 wafers per month, with the whole industry approaching 200,000 once outsourced partners are counted. So "200,000" may describe the industry, not TSMC alone.
  • The equipment lead-time figure (6 to 8 months, up from 3 to 6) comes from a post on X. A July rumor gave 7 to 9 months. Neither is confirmed by TSMC or its tool suppliers.
  • We did not find the Wei quote on package size in a primary transcript, so we cannot confirm his wording.

A short history of CoWoS price talk

Price stories about CoWoS recur, which is itself a reason for caution. In late 2024, TrendForce relayed a Morgan Stanley estimate that CoWoS prices might rise by 10% to 20%, depending on how much capacity TSMC added. In July 2026 the conversation moved to wafer pricing, with the Nikkei report of increases up to 10% from 2027. Now, in late October, a packaging-specific 20% number is back.

The pattern is that each cycle has a plausible direction, a headline figure that is hard to trace, and a company that declines to comment. Readers should weigh direction more than the exact percentage. A confirmed number would normally come through an earnings call, a customer's disclosed cost, or a named outlet quoting named sources.

Why this matters even if the exact number is wrong

Every credible source points the same direction: demand for AI packaging exceeds supply, and suppliers have pricing power. That has three practical consequences.

  1. Chip costs rise at the margin. Packaging is one slice of an accelerator's bill, alongside HBM and wafers. A 20% rise on that slice would not mean 20% dearer GPUs, but it adds to pressure that already showed up in memory. See how memory pricing moved a developer box in Nvidia's DGX Spark memory-cut price story.
  2. Alternatives get more attention. Designs that avoid HBM and advanced packaging, such as Intel's D270 GPU with 480 GB of LPDDR5X, look better as packaging gets pricier. So do sovereign CPUs such as Fujitsu's Monaka on TSMC.
  3. Compute prices stay sticky. Rental prices for GPUs have moved in both directions this year, as we covered when checking a claimed 45% drop in H100 rental prices. Upstream cost increases are one reason not to assume cheap compute keeps falling.

Packaging is not the only physical limit either. Our piece on 160-week transformer lead times shows grid equipment holding back data centers in the same way.

What this means for what you build or pay

  • If you buy API tokens: nothing changes today. Price cuts and increases at labs depend on far more than packaging, and a chip cost change takes quarters to reach list prices.
  • If you reserve GPU capacity: an increase in chip costs would show up first in new contracts for next-generation hardware. Watch quotes for 2027 deliveries and ask suppliers whether contracts include pass-through clauses.
  • If you plan on-prem or edge AI: favor designs and models that fit in cheaper memory and avoid the tightest supply lines. Smaller or quantized models help.
  • If you track the industry: the signal to watch is TSMC's own statements. Its earnings call is the most likely place for any confirmation, and company filings beat anonymous sources.

How to check this story yourself

  1. Search TSMC's investor relations page for earnings call transcripts and look for CoWoS pricing or capacity commentary.
  2. Look for the original supply-chain report behind the X posts. If it cites a named outlet, read that outlet's text, not the screenshot.
  3. Compare any figure against the July Nikkei and September supply-chain reports to see whether it is new or a repeat.
  4. Check whether ASE or Amkor, the outsourced packaging providers, have announced their own quotes, since their pricing often moves in parallel.

Bottom line

The direction is credible, the number is not confirmed. A TSMC price rise in 2027 is backed by a named Nikkei report at up to 10% on chipmaking; a CoWoS-specific 20% rests on unnamed sources, and TSMC refuses to comment on pricing. We will update this post if TSMC, Nikkei or another named outlet confirms a figure.

Related reading:

  • AI chip supply chain: TSMC record, Samsung, GlobalFoundries interposers
  • Nvidia's first US-made GB300 chips and Amkor packaging
  • Nvidia DGX Spark price and memory cut
  • Intel D270 GPU without HBM
  • Fujitsu Monaka sovereign AI CPU on TSMC
  • H100 rental price claim: claimed vs verified
  • 160-week transformer lead times

Reports are as of October 27, 2026; TSMC has not confirmed any figure and numbers may change.

Spotted something out of date? Let us know.
Yash Thakker

Written by

Yash Thakker

Yash is an AI expert with over 300K learners. Join his workshops →

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