Intel now has a product page for an AI card that bets against the industry's favorite memory. The Intel GPU D270 is described as an inference-optimized data center GPU with up to 480 GB of LPDDR5X per card, 350 W of air cooling and a standard PCIe 5.0 form factor. It uses no high bandwidth memory (HBM) at all.
The pitch is aimed squarely at the way AI workloads have shifted. Intel's page argues that agents "read far more than they write," with long contexts, multistep workflows and compute dominated by prefill. If that is your workload, capacity and cost per token matter as much as raw bandwidth, and Intel is selling capacity.
TL;DR: Intel GPU D270 at a glance
| Question | Answer from Intel's page |
|---|---|
| What is it? | Inference-optimized data center GPU, not a training part |
| Memory | Up to 480 GB LPDDR5X per card |
| Compute | 32 Xe3P cores, 256 XMX matrix engines |
| Power and cooling | 350 W, air-cooled, passive in existing racks |
| Interconnect | Standard PCIe 5.0, no proprietary networking |
| Precision | Native low-precision inference up to FP64 |
| Software | vLLM, open PyTorch ecosystem; FAQ also mentions SGLang and Triton |
| Price, bandwidth, benchmarks, ship date | Not published |
Why would anyone build an AI GPU without HBM?
HBM is fast and scarce. It sits on the package next to the compute die, supply is constrained, and it dominates the bill of materials of the accelerators that train frontier models. Intel's choice of LPDDR5X trades peak bandwidth for much more capacity per dollar and per watt.
Intel frames the benefit as keeping more of the model and long context resident, "for richer reasoning with fewer GPUs and no high bandwidth memory." In inference, the key-value cache grows with context length and with the number of concurrent sessions. A card with 480 GB can hold far more sessions or far longer contexts than a card with a fraction of that, even if each token is generated more slowly. Intel names the target scenario: over thousands of steps, 100K token contexts and dozens of concurrent sessions, keep agents resident to sustain throughput across the agentic loop.
This matters because HBM supply is a real bottleneck. We covered how memory makers are racing to fill it in Samsung's HBM4 yield claims. A card that does not need HBM sidesteps that queue, which is presumably part of the appeal for operators who cannot get allocation.
What is actually inside the card?
Intel says die area was reallocated away from graphics and ray-tracing pipelines toward Xe3P compute and matrix engines. The headline numbers are 32 Xe3P cores and 256 XMX matrix engines. Intel says that gives "more prompt processing per watt," accelerating prefill and curbing long-context and agentic costs.
Precision support spans native low-precision inference to FP64 scientific computing. The page's line is that the workload determines the precision, not the hardware. That is a notable contrast with inference-only ASICs that give up high-precision math.
Footnotes on Intel's page say performance projections against NVIDIA's RTX Pro 6000 are based on public information and Intel internal analysis as of February 2026, with memory capacity compared at comparable bandwidth. The page does not print the comparison numbers, so treat any comparative claim as unsubstantiated for now.
Is the D270 the same chip as Crescent Island?
Probably, but Intel's page does not say. At the 2025 OCP Global Summit, Intel unveiled Crescent Island, an Xe3P inference GPU with 160 GB of LPDDR5X, aimed at air-cooled enterprise servers, as TechRadar reported. A later report from the AI Weekly alert on Crescent Island, citing Tom's Hardware, described Computex 2026 coverage of an Xe3P data center inference accelerator with up to 480 GB of LPDDR5X and support from FP4 through FP64.
The architecture, memory type, positioning and air-cooling story line up with the D270. We would not treat the codename mapping as confirmed until Intel states it. The original plan was customer sampling in the second half of 2026 and general availability in 2027, per earlier reporting on the predecessor; the D270 page gives no dates.
Chips and data center towers illustrating air-cooled rack deployment of the Intel GPU D270
The trade-offs Intel is not putting on the page
Capacity is only half of inference performance. Token generation, the decode phase, is typically limited by how fast weights and cache can be streamed from memory. LPDDR5X delivers far less bandwidth per stack than HBM, and Intel has not published a bandwidth figure for the D270. Until it does, no one can say how fast a 400-billion-parameter model decodes on this card.
Prefill is where Intel's design is most credible. Prefill is compute-bound, which is what the 256 matrix engines are for, and agentic workloads that re-read large contexts spend much of their time there. Decode-heavy chat, in contrast, is where an HBM part should win.
Other open questions: price, how many cards fit in a server, whether multi-card scaling over PCIe 5.0 holds up for models that need more than 480 GB, and how mature Intel's software stack is on real models. Intel promises zero-day support for leading open models on vLLM and the open PyTorch ecosystem; the proof is in kernels, not slogans.
A back-of-envelope view of why capacity matters
Long context ribbon passing through a wide ring, showing long-context inference on an Intel GPU D270
The following is our illustration, not an Intel figure. Suppose a serving team runs a model whose weights occupy 200 GB in a compact format and wants dozens of concurrent agent sessions at 100K tokens each. Every session carries its own key-value cache, and that cache scales linearly with context length. Multiply a 100K token context by dozens of sessions and the cache alone can exceed the weights. On a card with 80 or 96 GB, the operator either shards the model across many cards, which adds interconnect cost, or evicts caches and recomputes prefill, which burns compute.
A 480 GB card changes the arithmetic: weights and a large fleet of caches can sit on one device, and sessions stay resident between agent steps instead of being rebuilt. That is exactly the scenario Intel's page describes when it talks about keeping agents resident. The price of this convenience is slower decode per session, which is why concurrency, not single-stream speed, is the metric to watch if you evaluate the card.
It also explains Intel's emphasis on prefill. Agents repeatedly feed large tool outputs, files and histories back into the model, so the share of work spent reading rather than writing is high. Matrix engines tuned for prompt processing make the most sense in precisely that regime. Whether the real-world ratio justifies the trade is an empirical question that only benchmarks on actual agent traces can answer.
How does it compare with other inference hardware we have covered?
Inference hardware is splitting into camps. Cerebras sells wafer-scale speed, which we looked at in the CS-4 claim of 30x faster inference. Microsoft is building its own inference silicon, summarized in our post on the Maia 300 and tokens per megawatt. NVIDIA keeps pushing rack-scale designs, as in its Vera Rubin open designs. The D270 occupies a different corner: modest power, standard servers, big memory, probably modest price.
| Approach | Example | Bet |
|---|---|---|
| Wafer-scale speed | Cerebras CS-4 | Lowest latency |
| Custom cloud silicon | Microsoft Maia 300 | Tokens per megawatt in one fleet |
| Rack-scale HBM | NVIDIA Vera Rubin | Maximum bandwidth |
| Capacity-first PCIe card | Intel GPU D270 | Fit more context per dollar and per watt |
For people running models at home or on a workstation, the closest analog is capacity-versus-bandwidth thinking in local rigs, as in Gigabyte's GB300 deskside workstation versus DGX Spark and antirez's DwarfStar local inference.
Who should care today?
- Inference platform teams weighing an alternative to constrained HBM supply, especially for long-context RAG, coding assistants and agent fleets.
- Sovereign-cloud and GPUaaS providers, two audiences Intel names explicitly in its FAQ, for whom standard PCIe servers and no liquid-cooling retrofit simplify deployment.
- Developers choosing a serving stack. The practical message is that Intel is committing to vLLM and PyTorch, so a serving config written today should not need to change.
- Everyone else can wait: no price, no benchmarks and no shipping date means this is a signal about direction, not a purchase.
What to watch next
- A published memory bandwidth number and third-party decode benchmarks.
- Performance per watt and per dollar versus HBM parts on long-context workloads.
- Whether Intel confirms the Crescent Island lineage and names the sampling and availability schedule.
- Real vLLM results on open models with cards in customers' hands.
Bottom line
The D270 is a clear statement of strategy: when agents hold long contexts across many sessions, memory capacity and power draw can matter more than peak bandwidth, and Intel will sell the capacity side of that argument without HBM. It is promising on paper, light on published numbers. Treat it as a hardware direction to track until benchmarks and pricing arrive.
Related reading
- Cerebras CS-4 wafer-scale accelerator
- Microsoft Maia 300 inference chip
- NVIDIA Vera Rubin open designs
- Samsung HBM4 yield
- Gigabyte GB300 deskside vs DGX Spark
- DwarfStar local inference
Specifications reflect Intel's product page as read on October 13, 2026 and may change.