Nvidia's Vera CPU now has independent measurements. Chips and Cheese published a deep look at Vera's system architecture, and the headline is a split verdict: memory bandwidth and cache are large steps up from Grace, while latency between cores and sockets is the soft spot. Local memory latency stays at or under 200 ns even as bandwidth load climbs, according to the article by Chester Lam.
It is the first outside check on the figures Nvidia gave in its marketing. In August we covered the Vera whitepaper and its marketing problems; this is the measured follow-up.
Quick reference: Vera by the numbers
| Item | Nvidia's page | Chips and Cheese measurement |
|---|---|---|
| Cores | 88 Olympus cores, 176 threads | Olympus cores aimed at high per-core performance |
| Memory | LPDDR5X on SOCAMM, up to 1.5 TB | 1024-bit LPDDR5X-9600, up to 1.228 TB/s |
| Memory latency | Not stated on the page | Local under 200 ns |
| On-die fabric | 2nd-gen Scalable Coherency Fabric, 3.4 TB/s bisection | Likely a mesh; each node hosts a pair of cores |
| GPU link | NVLink-C2C up to 1.8 TB/s | 1.8 TB/s theoretical cross-socket |
| I/O | Not itemized here | 88 PCIe lanes, 665.5 GB/s |
| L3 cache | Not itemized here | 164 MB shared, non-inclusive, 3.35 TB/s read |
| Cross-socket latency | Not stated | 309.27 ns |
Sources: Nvidia's Vera CPU page and the Chips and Cheese article. Treat every Chips and Cheese figure as one author's measurement on the hardware they had, not an official spec.
What is inside the chip?
Four nodes joined by a woven lattice, illustrating the mesh fabric inside the Nvidia Vera CPU
Per the article, Vera connects its cores, cache and I/O with a second-generation Scalable Coherency Fabric. A Coherency Switch Node hosts a pair of cores, a layout also used by Ampere's Altra Max. Memory Switch Nodes bridge the fabric to the LPDDR5X controllers, and Bridge Switch Nodes host the PCIe controllers and the cross-socket link.
Nvidia's page describes the same fabric as connecting all cores, cache, memory, I/O and NVLink-C2C on a single compute die. That matches the measured picture of a large mesh, and it explains the pattern in the latency results below: a big mesh gives high shared bandwidth at the cost of longer paths between far-apart agents.
Where Vera sits in the Grace to Vera lineage
Grace, Nvidia's first server CPU, was built to feed Hopper and Blackwell GPUs with coherent memory over NVLink-C2C. It did that job but had a reputation for modest single-thread speed. The Chips and Cheese article notes Grace's 1 MB L2 caches and high memory latency as the baseline Vera improves on. Vera doubles the L2 per core to 2 MB, and moves to the custom Olympus core with an LPDDR5X-9600 memory interface.
That history explains the design bet. Nvidia is not trying to win a many-core cloud race against chips with far more cores. It is trying to make the CPU half of a GPU system stop being the slow part: faster individual cores, a very wide memory pool, and a coherent link to Rubin. The article's conclusion, that Vera trades core count for per-core performance and bandwidth, fits that story. Whether the trade is right depends on whether your job looks like a GPU feeder or like a general cloud workload.
What are people asking about Vera?
Is the 88-core count small? Next to Graviton 5, yes, and that is why Graviton 5 wins at the socket level in the throughput tests. Vera's argument is per-core speed and bandwidth per core.
Can I upgrade the memory? Per Chips and Cheese, the SOCAMM2 modules are serviceable and upgradeable, and Nvidia's page calls the modules detachable and field-replaceable. That differs from soldered LPDDR in most laptops and many servers.
Does the high cross-socket latency hurt GPU training? The article does not test GPU workloads, so there is no measurement to point at. The latency affects CPU-side thread sharing, not the GPU interconnect.
Is there an independent check of Nvidia's 1.8x claim? Not that we found. The SPEC runs in the article are a different test from Nvidia's agentic sandbox benchmark.
How good is the memory system?
This is Vera's best result. The 1024-bit LPDDR5X-9600 interface gives up to 1.228 TB/s, and the SOCAMM2 modules are serviceable and upgradeable, which is unusual for LPDDR-based designs. Chips and Cheese found local latency under 200 ns that stays steady as bandwidth load rises, which is the behavior that matters for streaming workloads.
Nvidia says the design offers about twice the bandwidth of conventional CPU memory at half the power, and roughly 3x bandwidth per core versus x86 with DDR5. Those are Nvidia's claims, and its page says the comparison data can change and does not name the x86 baselines. The measured 1.228 TB/s matches Nvidia's headline figure, which is the part we can say is confirmed. The "half the power" and "twice" comparisons are not something the article tests.
Cache: a big improvement over Grace
Chips and Cheese describes a shared 164 MB L3 that is non-inclusive, with 2 MB of L2 per core, for up to 340 MB of effective capacity. Total L3 read bandwidth is about 3.35 TB/s, or 33.1 GB/s per core when all cores load it, down from 88.5 GB/s for a single uncontended core.
Against AMD's Genoa-X, per-core L3 bandwidth is higher on the AMD part (about 85 to 90 GB/s) but its L3 is split into per-cluster slices, so a core only sees its own slice. Vera's cache is one shared pool. The article calls the design a clear improvement over Grace, which had 1 MB L2 caches and high memory latency.
Where does Vera lose?
Cross-socket memory latency
In a dual-socket setup, cross-node latency measured 309.27 ns, which is 177.41 ns above local access. An isolated pointer-chase test exceeded 370 ns. Reads reached about 587 GB/s across the link and read-modify-write reached 780 GB/s, though latency can spike to 780 ns under that load. AMD's Genoa-X measured 222.7 ns cross-socket in the same comparison.
Core-to-core latency
Same-socket core-to-core latency averages 148.5 ns, ranging from 87.5 to 199.3 ns. SMT siblings are under 10 ns. Across sockets it is about 660 ns, which the author calls high, against about 209 ns on Genoa-X; Graviton 4 is better still.
Why that matters: lock handoffs, message passing and work stealing between threads pay the core-to-core price. Parallel jobs that share data across cores, especially across sockets, will feel it more than streaming jobs.
How does it compare on SPEC CPU2026?
Chips and Cheese ran SPEC CPU2026 throughput. The article's summary: Vera beats Graviton 5 node for node and beats a Zen 5 configuration. At the socket level it trails Graviton 5, which packs more cores. In memory-bound workloads such as 749.fotonik3d, Vera leads Graviton 5 by about 20%. Graviton 5 wins clearly on cache-friendly workloads.
The conclusion matches the architecture. Vera trades core count for per-core performance and memory bandwidth. It suits workloads where individual tasks must be fast, or that are bandwidth-bound.
| Workload type | Likely better fit (per the article) |
|---|---|
| Memory-bound, streaming | Vera |
| Cache-friendly, many threads | Graviton 5 |
| Heavy cross-socket thread sharing | Genoa-X, based on latency |
| Feeding Rubin GPUs over NVLink-C2C | Vera by design, though the article did not test GPU pairing |
Why does an AI CPU matter now?
AI infrastructure has been talked about as a GPU story, but agent workloads add CPU-heavy work: sandboxes, tool execution, orchestration and data prep. Nvidia's own claim is that Vera runs agentic sandbox workloads up to 1.8x faster than leading x86 CPUs, though it does not publish the baselines. The CPU market is reacting. AMD has pushed a CPU rack aimed at agentic AI, and Intel has shown a GPU with 480 GB of LPDDR5X and no HBM, so LPDDR memory is the common thread.
For readers choosing hardware, the practical read:
- Bandwidth-bound inference or data pipelines on CPU: Vera's 1.2 TB/s is the number to compare against.
- Many-thread, shared-state software: check cross-socket latency before betting on dual-socket Vera.
- Cloud buyers: the comparison to Graviton 5 shows Arm cloud CPUs are close; throughput per dollar, not per socket, will decide.
- GPU-attached deployments: the real selling point is NVLink-C2C coherence with Rubin GPUs, covered in our posts on Nvidia's open Vera Rubin designs and the first Vera Rubin cluster at CoreWeave. The Chips and Cheese article does not measure that pairing.
What this does and does not prove
Confirmed by measurement (one outlet): bandwidth near 1.228 TB/s, sub-200 ns local latency, the cache sizes, and the cross-socket and core-to-core latencies above.
Not confirmed: Nvidia's 1.8x agentic sandbox speed-up, the "half the power" claim, and any end-to-end GPU workload result. The article is a single independent source; wait for more measurements, ideally on production systems, before treating the SPEC comparison as settled.
Also note that SPEC results depend on compilers, configuration and system tuning, and the article compares particular configurations of Graviton 5 and Zen 5. Read the original for the exact setups.
How to read the next Vera claim
When a vendor quotes a speed-up, ask three things: what is the baseline, is it per core or per socket, and is the workload bandwidth-bound? Vera's measured profile suggests it wins when the answer to the last question is yes, which is why the results look strong on 749.fotonik3d and weaker on cache-friendly code. Our AI infrastructure summit coverage has more on where Nvidia positions Vera in the Rubin platform.
Specs and measurements reflect Nvidia's product page and the Chips and Cheese article as of October 20, 2026.