DeepX DX-M2 Tape-Out: 100B Parameters at Under 5 Watts, Claimed vs Verified

DeepX, a South Korean edge-AI chip company, has reportedly taped out its second-generation DX-M2 processor. The company says the chip can run language models of 20B to 100B parameters at under 5 watts, for robots and drones. None of the performance numbers has been measured on silicon in public. Samples are targeted for March 2027 and mass production for fall 2027.

This post separates what is confirmed from what is claimed. The short version: the tape-out is reported by EE Times, the specifications come from DeepX, and the headline "100B at 5W" only works for a specific kind of model.

TL;DR: claimed vs verified

What did DeepX actually say?

At CES in January 2026, DeepX unveiled the DX-M2 roadmap. Its release says the DX-M2 is "designed to run Large Language Models (LLMs) of up to 100 billion parameters at under 5 watts." The roadmap targets on-device inference for 20B to 100B parameter models, including mixture-of-experts (MoE) architectures.

DeepX Vice President Young Cho said: "Running a 100B parameter LLM under 5 watts isn't just a performance upgrade." The release goes on to say it reshapes what is possible for AI infrastructure. The company also forecast that moving inference to edge devices could cut data center traffic by more than 80 percent. That is a forecast, not a result.

The release describes the first-generation DX-M1 as deployed in over 50 projects across robotics, defense and industrial sectors, and says the DX-M2 builds on lessons from that mass production. The DX-M1 is a vision chip. The DX-M2 is the company's first attempt at language models.

What is new this week?

According to a November 9 write-up that cites EE Times, DeepX has taped out the DX-M2. The reported specifications are:

• A 2nm-class process. A January EE Times Japan report said the design uses Samsung's 2nm-generation GAA process with four NPU cores.
• 80 TOPS of compute and 150 GB/s of memory bandwidth, under 5W.
• A stated range of 10 to 30 tokens per second on 20B to 100B parameter models.
• A pairing with Samsung's LPDDR5X processing-in-memory (PIM), where simulation projects a 6.7x throughput gain on Llama 3.1 8B at 2.7x the power.
• Samples in March 2027 and mass production in fall 2027, aimed at robots and drones.

We could not open the EE Times original. Everything above about the tape-out comes from summaries that cite it, so treat the exact wording as second-hand. One secondary report also notes that tape-out is a milestone toward a product, not proof that the chip reaches its targets.

Does the math support 100B parameters at 10 to 30 tokens per second?

Stack of memory blocks with one fitting a slot, showing why a DeepX DX-M2 100B model is a memory problem

Generating text is mostly limited by memory bandwidth, not compute. Each new token requires reading the model's active weights from memory. A rough ceiling is bandwidth divided by bytes read per token.

This is our arithmetic, using DeepX's stated 150 GB/s and common 4-bit quantization (half a byte per parameter):

Two conclusions follow. First, "100B parameters" and "10 to 30 tokens/s" can both be true only for a sparse MoE model that activates a small slice of its weights. A dense 100B model would crawl at a few tokens per second on 150 GB/s. Second, the whole 100B model still has to fit in memory: about 50 GB at 4 bits. That memory is not on the chip, so board cost, size and power for the memory are separate questions the "under 5W" figure may not cover. Whether the 5W figure includes the DRAM is not stated in the sources we read.

DeepX's PIM pairing is an attempt to attack this bottleneck by doing part of the matrix-vector work inside the memory. The only number offered is a simulation on an 8B model.

Why does this matter for robots and drones?

Tiny core inside a sensor housing, an edge AI chip running inside a robot or drone

The DX-M2 is aimed at machines that cannot rely on a network link or a large battery. A language or action model running locally removes round-trip latency and keeps working when connectivity drops. This is the same "physical AI" direction we have followed in robot foundation models, such as Gemini Robotics 2.5 in a Mercedes kitting trial and the LeRobot 0.7.0 release.

A chip is only useful with models that fit it. Open on-device models are arriving: see our coverage of Edge0 145B for laptop agents. Whether those run on the DX-M2 depends on DeepX's software stack, which the sources do not detail.

How does this compare with other edge and local-AI claims?

Hardware vendors regularly pitch large-model edge inference. Qualcomm's chief executive said AI labs want 100B-parameter phones by 2028; we checked that claim against memory math and reached a similar conclusion: size is a memory problem first. At the other extreme, Cerebras' wafer-scale CS-4 targets data centers with vastly more bandwidth. The DX-M2 sits between: a very low power budget, modest bandwidth, and a bet on sparse models.

What does tape-out mean, and why is it not a product?

Tape-out is the point where a chip design is finalized and its masks are sent to the foundry. It is a real engineering milestone: the design has passed verification well enough that the company is willing to pay for manufacturing. It is not the end of the road. The first silicon still has to come back, be powered up, and be tested. Teams then find bugs, adjust clocks and voltages, and sometimes respin the design.

Only after that bring-up can a company publish measured numbers. For the DX-M2, that means the 80 TOPS, 150 GB/s and under-5W figures are design targets until measured parts exist. The March 2027 sample date leaves several months for that work, and the fall 2027 production target leaves little slack if a respin is needed.

For a buyer, the practical questions are different from the headline. Can you get a dev kit? What compiler flow turns a model from a common format into something the NPU runs? How does the chip handle long contexts, where the key-value cache adds memory traffic on top of the weights? DeepX's earlier CES release lists an "AI Player" dev kit and partnerships with Ultralytics and Baidu PaddlePaddle for the first-generation vision chip. None of the sources we read says how language-model support will reach developers.

What is still missing

Before you plan around this chip, look for these:

1. A measured demo. No public silicon benchmark exists yet. Sample units in 2027 would be the first chance for independent tests.
2. Model and toolchain support. Which MoE models, which quantization formats, and how a developer compiles them.
3. The real power figure. Whether "under 5W" covers the chip alone or the whole module with memory.
4. Price and availability. Not stated in the sources. A Japanese sample reservation process exists, but a reservation is not an order or a delivery guarantee, and pricing and final specifications are not fixed.
5. Schedule risk. A January report said mass production could start at the end of 2026. The current target is fall 2027.

One mismatch is worth flagging. An analyst site described the chip as still at concept stage earlier, and another page lists a tape-out around March 2027. The November reports say tape-out is done and samples come in March 2027, so the March date likely refers to samples. We are following the more recent, mutually consistent reports.

How to read future claims like this

A useful checklist when a chip vendor says it can run a very large model at very low power:

• Ask whether the model is dense or MoE, and how many parameters are active per token.
• Ask what quantization is assumed, and where the weights live.
• Ask whether the power figure includes memory and the host.
• Ask for tokens per second at a stated context length, on a named model.
• Separate simulation results from silicon measurements.

Applied here, the DX-M2 passes the first test only for sparse models, and fails the last two so far because nothing is measured.

Bottom line

DeepX has a real chip program, a public roadmap and a reported tape-out. It has not shown a working 100B-class demo, and its own timeline has slipped. If you build robots or drones, the sensible move is to note the March 2027 sample date, plan around sparse models in the 10B to 30B active range, and wait for independent measurements.

Related reading

• Qualcomm: 100B-parameter models on phones by 2028
• Cerebras CS-4 wafer-scale accelerator
• Edge0 145B open on-device model
• Gemini Robotics 2.5 and Mercedes kitting
• LeRobot 0.7.0 guide
• Official: DeepX CES 2026 roadmap release

Specifications and dates are accurate as of November 13, 2026 and come from DeepX and secondary reports; they may change.