PCBRouteAgent: LLM Agents That Plan PCB Routes in KiCad

PCBRouteAgent asks a practical engineering question: can a large language model agent plan printed circuit board routes well enough to pass official design-rule checks, without micromanaging every geometric push in KiCad? The arXiv paper 2611.08175, public project site, and GitHub repository released in early November 2026 say the answer is yes on many small and medium boards, with large boards still fragile.

The framework is not a new foundation model. As the submitter noted on Hugging Face Papers, PCBRouteAgent orchestrates existing LLMs around KiCad native routing. That makes it a complement, not a duplicate, to Anthropic Fable 5.2 electronics demos and Build-A-Chip-Bench agent scores that measure broader chip-design tasks.

TL;DR

What PCB routing agents must actually do

Routing runs after placement. The agent receives a KiCad board with fixed components, a netlist, and design rules, but target copper is removed. It must reconnect pads with traces and vias without violating clearance or width limits.

The authors judge success with the PCBWorld evaluator: required nets must be complete and KiCad must report zero error-level design rule violations. A pretty screenshot is insufficient. That bar matches how human layout engineers are graded in production, and it is stricter than completion-only agent demos.

PCB routing agent input board with components and output copper traces for LLM-assisted electronic design automation Image: chip-ai-agent

Global planning versus KiCad execution

Green microchip connected to branching circuit traces illustrating LLM-guided PCB routing automation

Early LLM tool loops tried to issue one geometric action per model call. On dense boards that explodes latency and context, and a locally good trace can block a later net globally.

PCBRouteAgent copies how senior layout engineers work:

1. Global Routing Planner reads structured board data plus images, then sets connection topology, order, soft corridors, and layer hops.
2. Detailed Routing Executor realizes those guides with KiCad push-and-shove geometry and bounded local recovery.
3. Feedback-driven replanning sends structured failure evidence back to the planner when recovery exhausts its budget.

PCBRouteAgent global planner KiCad executor and feedback replanning for automated PCB routing with LLM agents Image: chip-ai-agent

The LLM does not draw every vertex. KiCad handles physics-aware pushes; the model revisits decisions that need board-level foresight, such as reserving corridors before routing sensor power.

Benchmark numbers on PCBWorld-Bench

The evaluation spans 247 boards across four splits published in PCBWorld. The Opus variant hits 100%, 94.9%, 100%, and 40% clean pass on D2, D3-A, D3-B, and D3-C respectively.

On the three real-world subsets, that is 13.9, 36, and 10 percentage points above the strongest evaluated baselines named in the paper tables. D2 synthetic boards saturate at 100% for both top agents and classic routers, so the interesting signal is D3 real hardware.

Routability and violation counts tell a sharper story on D3-A. Mean routability rises from 0.900 to 0.994, while mean design-rule violations fall from 1.08 to 0.09 versus Freerouting in the project tables. On D3-C, mean violations drop 80.3%, yet only four of ten boards achieve full clean pass, which shows how harsh the evaluator is on large designs.

Cost: 131× fewer model calls with Haiku

Holding the backbone fixed at Claude Haiku 5.5, the authors compare PCBRouteAgent against PCBWorld interactive agents. Clean pass jumps from 34.3% to 92.9% on D3-A, from 0% to 80% on D3-B, and from 0% to 10% on D3-C, supporting the claim that architecture, not only model size, drives gains.

Across all 247 boards, PCBRouteAgent averages 172 model calls versus 22,529 for PCBWorld Haiku, about 131× fewer. Combined token use falls roughly 8.8×, API cost about 4.3×, and wall-clock about 14× in their accounting. Many boards finish after scripted guide initialization without a model revision, which explains sub-one-call averages on easy splits.

Case studies: where engineers still win

The project site documents three instructive failures, not just leaderboard wins.

More routing from fewer calls. On one D3-C board, PCBWorld Haiku connects 10 of 86 targets before hitting its step cap, while PCBRouteAgent connects 84 of 86 with five model calls. Token use drops more than 80%, yet two nets remain open, so completion improved without a clean pass.

Early routes trap later signals. Another D3-C board routes sensor power first without reserving pad access. Later clock and data nets stall because the kept power trace blocks vias. The authors conclude local retries cannot fix a bad global allocation, echoing manual layout reviews.

Connectivity without electrical intent. On D3-B, an Opus run connects all 55 targets but routes USB D+ and D− independently instead of as a controlled differential pair like the human reference. The planner lacked explicit pair constraints, so DRV-clean connectivity still misses signal integrity rules engineers enforce.

Those cases matter for builders evaluating EEBench-style circuit tasks or ArchGen Newton physical design agents. Passing automated DRC is necessary, not sufficient, for shipping hardware.

How to try the framework

Clone chip-ai-agent/PCBRouteAgent and follow its environment setup for KiCad interaction. Expect API spend on global replans, not on every push.

You will need:

• A KiCad installation compatible with the executor scripts
• API access to the LLM backbone you choose (Opus variants score highest in the paper tables)
• PCBWorld-Bench splits if you want apples-to-apples comparisons with published baselines

Because weights are not bundled, swaps are straightforward: rerun with a newer Claude or another multimodal model and compare clean-pass rates on your own boards.

Relationship to Anthropic and NVIDIA agent research

November 9 also brought Claude Fable 5.2 device design stories where partners manufacture working prototypes from model-generated schematics. PCBRouteAgent zooms into one automation step, automated copper routing with measurable DRV outcomes.

NVIDIA ChipAgents and Build-A-Chip-Bench measure end-to-end silicon tasks at low double-digit success rates. PCBRouteAgent shows that when you bind agents to native EDA engines, PCB routing can clear 90%+ clean pass on small real boards even if large boards remain at 40%.

For software teams without fabs, the lesson is the same pattern AWS and Anthropic keep preaching: specialists execute, planners reason, feedback loops reopen strategy. Our AWS seven-layer agent framework post names that split for enterprise IT; PCBRouteAgent implements it for copper.

Limits and honest next steps

Large boards still fail more often than small ones. Wirelength can rise versus Freerouting while completion improves, so cost-aware layout engineers may reject some winning traces.

The framework does not replace analog tuning, thermal planning, or EMI review. Differential pairs, length matching, and high-speed constraints need explicit representations in the planner, not implicit hope from DRV checks.

Reproducibility will depend on KiCad versions, API pricing, and whether PCBWorld-Bench splits stay fixed as authors publish updates. Treat leaderboard percentages as research signals, not vendor warranties.

PCBWorld splits and what each one tests

The authors inherit PCBWorld splits with different difficulty profiles. D2 holds 128 synthetic boards where classic routers already reach perfect clean pass; agents mainly prove they do not regress on easy topology. D3-A is the workhorse set with 99 small real-world boards where Freerouting sat at 81% clean pass before PCBRouteAgent lifted the bar into the mid-nineties.

D3-B and D3-C are tiny but punishing counts of medium and large real boards. A ten-board split means one stubborn design moves the percentage by ten points, so read D3-C as directional, not a production SLA. The manuscript is explicit that D3-C Opus still leaves six of ten boards failing full clean pass even when mean violations fall sharply.

Baseline naming in the tables also deserves care. Reference scores retain original human-routed designs rather than running an automatic router, so it is not a fair automation competitor. The paper excludes Reference when calling out the best evaluated baseline, which keeps comparisons focused on Freerouting, KiCadRoutingTools, and PCBWorld reinforcement-learning agents rather than cherry-picked golden layouts.

Tooling stack inside the executor

KiCad push-and-shove routing handles collision pushes, via placement, and layer transitions under design-rule checks. PCBRouteAgent treats that engine as authoritative geometry: the LLM proposes corridors and ordering; KiCad enforces manufacturability. When local recovery exhausts its budget, structured feedback returns which nets failed, what clearance blocked progress, and which earlier routes might need revision.

That division is why call counts can drop below one per board on easy splits. Script-generated initial guides plus native execution finish without model intervention until a congested region triggers replanning. Hard splits flip the ratio: D3-C Opus runs still spend hundreds of seconds when guides iterate.

For teams comparing against interactive agent baselines, note PCBWorld Haiku issues one model call per low-level action in the paper accounting, which explodes cost on dense boards. PCBRouteAgent's planner-centric loop is the economic story as much as the accuracy story.

What developers should watch

If you build hardware copilots, track three metrics on your own boards:

1. Clean-pass rate, not just connected nets.
2. Model calls per board, because global replanning dominates COGS.
3. Constraint classes missed, such as differential pairs, which DRV alone will not catch.

Agents that only chat about schematics will not survive procurement review. Agents that emit verifiable KiCad artifacts with cited evaluator logs might.

Related reading

• Claude Fable 5.2 PCB and electronics design with Diode
• Build-A-Chip-Bench and ChipAgents scores
• EEBench circuit design evaluation
• ArchGen Newton physical design agent
• OpenAI BenchCAD and physical engineering agents
• AWS seven-layer Pluggable Agentic AI Framework
• CloudOpsBench Fable versus Astra on ops tasks